1. Field of the Invention
The present invention relates to a digital filter and a digital signal processing system using a digital filter, such as a waveform equalizer, for filtering image signals, acoustic signals or the like.
2. Description of the Prior Art
Finite impulse response (FIR) digital filters have two types of structures as shown in FIGS. 1 and 2. FIG. 1 shows a prior art n-tap digital filter of the direct type structure, wherein reference numerals 61(1)-61(n-1) denote delays, reference numerals 62(1)-62(n) denote multipliers and reference numerals 63(1)-63(n) denote adders. In the direct type circuit structure shown in FIG. 1, an input data is delayed directly by the delays 61(1)-61(n) successively. The input data and the delayed data in each tap is multiplied by the prescribed coefficient by the multiplier 62(1)-62(n). The products of the multiplication at the n taps are summed successively by the adders 63(1)-63(n). In the first adder 63(1), the delayed signal is added to zero, while in each of the other adders, the output of the adder in the preceding tap is added to the input delayed signal in the tap. The total sum is output by the adder 63(n) at the n-th tap.
On the other hand, FIG. 2 shows a prior art n-tap digital filter of the inverted type structure, wherein reference numerals 61(1)-61(n-1) denote delays, reference numerals 62(1)-62(n) denote multipliers and reference numerals 63(1)-63(n) denote adders. In the inverted type circuit structure shown in FIG. 2, an input signal is multiplied by the multipliers 62(1)-62(n) by prescribed coefficients and the product of the multiplication is delayed by the delays 61(1)-61(n-1) successively.
The delays in the direct type structure are used for input data, while those in the inverted type structure are used to delay the result of the multiplication and the addition. Therefore, the bit width of the delays of the inverted type is wider than that of the direct type by the bit width of a multiplication coefficient for the multiplier. Therefore, the direct type structure is more advantageous due to a smaller number of the components used in the circuit of the digital filter.
However, in the direct type structure, it is difficult to add the results of multiplication of the number of "n" within one clock period. Further, if the above-mentioned operation is processed with a pipeline structure, the layout of the digital filter is difficult to design. That is, in a direct type digital filter made of many taps, it is impossible to add the results of each multiplication within one clock. As to the layout, if the multiplication results are collected to one position for the addition, the area required for circuit design becomes larger, and a full-custom design thereof is troublesome and inappropriate.
On the other hand, in the inverted type structure, it is possible to arrange basic units in an array regularly where a basic unit includes the multiplication and addition in one tap. Further, the delays also act as pipeline transistors for the addition operation. Then, the inverted type structure is appropriate for pipeline processing. Therefore, though the inverted type digital filter has larger components, it is adopted for most of custom chips.
A digital signal processing system such as a waveform equalizer system can be constructed with use of an FIR digital filter. FIG. 3 shows an example of a waveform equalizer system with the inverted type n-tap digital filter, wherein reference numerals 67(3)-67(n) denote delays, reference numeral 65 denotes a selector and reference numeral 66 denotes a controller for controlling the selector 65 and the multiplication coefficients of each tap.
In a digital signal processing system such as a wave equalizing system, the output of the digital filter is not provided until each multiplication coefficient is determined, and it is needed to output the input signal itself. The phase of the output of the input signal is needed to be matched with that of the output of the digital filter. Therefore, delays 67 are needed for the matching of the phase with the input signal. However, the delays 67 make the circuit size large.
As described above, the inverted type structure is used from the view points of the pipeline processing and the easiness of the layout though the direct type structure is more advantageous from the viewpoint of the number of components. If the inverted type structure is adopted, the reduction of the number of the components has a lower limit.